A Fully Differential High-speed Low Voltage Double-edge Triggered Flip-flop (detff)
نویسندگان
چکیده
In this paper, a high-speed double-edge-triggered flip-flop designed in 0.18μm CMOS technology is presented. Flip-flops, to a large extend, determine the speed of synchronous systems. The proposed flip-flop can operate with a clock rate as high as 12.5GHz, which translates to 25GB/s data rate. It samples the data on both edges of the clock. All signals are realized differentially. The differential output swing is 0.8V with a 1.8V power supply. The average power consumption is 7mW. A performance comparison between the proposed flip-flop and a single-edge triggered flip-flop realized in the same technology is also presented.
منابع مشابه
A Single Latch, High Speed Double-edge Triggered Flip-flop (detff)
This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered...
متن کاملA dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application
In this paper, a low voltage dual-pulse-clock double edge triggered D'flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistor...
متن کاملA novel low power and high speed double edge explicit pulse triggered level converter flip-flop
One of the effective ways to reduce power consumption is using clustered voltage scaling technique. The level converter flip-flop is needed to control static current when the block with Low Supply Voltage (VDDL) drives the block with High Supply Voltage (VDDH). One of the big challenges of design is that level converter flip-flop has low power and high speed. In this paper, pulse triggered leve...
متن کاملDesigning of Low Power Dual Edge - Triggered Static D Flip-Flop with DETFF Logic
The normal D flipflop consumes very high power. So in this paper we enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 90nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to static output-controlled discharge Flip– Flop (SCDFF). SCDFF involves an explicit pulse generator and a latch that capture...
متن کاملDual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power Applications
Pulse-triggered flip-flops are mainly used to improve speed of operation (pipeline speed), though flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Usually pulse-triggered flip-flops have specific structures and transistor sizes to optimize the system performance. The transistor size, topology, and threshold voltage of the flip-flop make the timi...
متن کامل